The present invention relates generally to integrated circuits with vertical trenches, and more specifically to integrated circuits having vertical trenches and complementary devices.
The investigation of parasitic vertical MOS transistors resulting from trench isolated lateral CMOS processes is described in Abstract No. 274, "Characterization of the Lateral and Vertical Parasitic Transistors in a Trench Isolated CMOS Process", M.C. Roberts et al., pp. 411-412. This articles indicates that the parasitic vertical MOS transistors will either not operate because of the voltages of the circuit or can be minimized by appropriate well doping and side wall oxide thickness.
Parasitic MOSFETs have also been investigated in "MOSFET Achieved by a Combination of Polysilicon Sidewall and SIMOX Technology", T. Ohno et al., Electronic Letters, pp. 559-560, May, 1986. The multi sidewall isolation layers of SiO2, polysilicon and field SiO2 and bottom isolation by by higher oxygen-doped polysilicon and buried oxide act as shield and traps for radiation induced charges.
The problem is further increased for devices which are subjected to irradiation. Vertical trench and vertical trench in combination with silicon on insulator (SOI) integrated circuits, although having some advantages have problems of increase in subthreshold leakage currents, threshold voltage shifts, and transconductance degradation by ionizing radiation. For N channel MOSFETs, it is especially important to eliminate the serious problems of increased leakage current caused by side and back or bottom channel conduction due to radiation induced positive charges trapped in the field-silicon dioxide layer and the buried oxide layer, one solution was discussed previously. Another solution is to fill the vertical trenches with a thin gate oxide and polycrystalline silicon semiconductor material and biasing the polycrystalline to turn the parasitic MOS device off. This may be sufficient in a single device conductivity circuit, but in a complementary circuit, wherein N and P devices are included, biasing the polycrystalline to either the positive or negative supply terminal will tend to turn either the parasitic NMOS off and the parasitic PMOS on or vice versa. Thus, this is not a solution for complementary circuitry.
Thus, an object of the invention is to provide radiation hardened integrated circuits including complementary devices.
Another object of the present invention is to provide a method of fabricating an integrated circuit having radiation hardened complementary devices.
An even further object of the present invention is to provide a circuit method of fabricating an integrated circuit having vertical isolation trenches and complementary devices which are radiation hard.
A still further object of the present invention is to provide a circuit and method of fabricating an integrated circuit having complementary devices on a silicon-on-insulator substrate and lateral dielectrical isolation trenches which is radiation hard.
These and other objects of the invention are attained by providing in the lateral trenches vertical gate segments separated from the lateral edge of the trenches by a dielectric gate layer and being connected at the bottom of the trench to doped device region. In a preferred embodiment the vertical gate segments are semiconductor material having the same doping as the doped device region in the bottom of the trench. The trenches are further filled with dielectric isolation to separate the gate segments from each other.
To reduce the parasitic capacitance, the vertical gate segment is provided only between two heavily doped regions of one conductivity type, separated by a lighter doped region of another second conductivity type, where all three regions terminate at the vertical edge of the trench. Although the planar devices described in the specification are directed to CMOS transistors, the invention is applicable to resistors, capacitors or any other device or devices forms of multiple semiconductor regions.
The method of fabrication includes forming the isolation trenches, covering the lateral walls with a dielectric insulative layer, followed by forming vertical semiconductor gate segments which are connected to the silicon at the bottom of the trench. The trenches are then filled with insulative material and planarized. The isolated islands and their adjacent vertical semiconductor gate segments are then doped with common conductivity type impurities. Surface regions of the opposite conductivity type than the previously formed regions are then formed. The dielectric insulative layer and semiconductor gate segments are applied by forming appropriate layers and then selectively removing, for example by reactive ion etching. The dielectric insulative layer at the bottom of the trenches is removed either totally, or selectively, prior to applying the semiconductor layer.
To form semiconductor gate segments only adjacent portions of the trench, the trench formation initially only forms the semiconductor gate segment portions of the trench with subsequent trench formation after the formation of the insulative layer and semiconductor gate regions. Where the substrate includes a buried insulative layer, the initial trench formation terminates prior to reaching the buried region. The removing of the semiconductor layer to form the vertical semiconductor gate portions continues to further increase the depth of the trench down to the buried insulative layer.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.